![]() Here in this paper we implemented 8, 16 and 32-bit LFSR on FPGA by using VHDL to study the performance and analysis the behavior of randomness. As it is simple counter so it can count maximum of 2n-1 by using maximum feedback polynomial. The total number of random state generated on LFSR depends on the feedback polynomial. As FPGAs is used to implement any logical function for faster prototype development, it is necessary to implement the existing design of LFSR on FPGA to test and verify the simulated & synthesis result between different lengths. It is more important to test and verify by implementing on any hardware for getting better efficient result. LFSR based PN Sequence Generator technique is used for various cryptography applications and for designing encoder, decoder in different communication channel.
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